DK-DEV-5SGXEA7N【PDF 87/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51005

2014.01.10

PLL Locations in Stratix V Devices

4-17

Figure 4-17: PLL Physical Counters Orientation for Stratix V Devices

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

PLL0

Physical Counter C0

Physical Counter C1

PLL1

Physical Counter C17

Physical Counter C16

Physical Counter C8

Physical Counter C9

Physical Counter

C0 to C17

(Up-to-Down

Physical Counter C9

Physical Counter C8

Physical Counter

C17 to C0

(Down-to-Up

PLL1

Physical Counter C16

Physical Counter C17

Dequence)

PLL0

Physical Counter C1

Physical Counter C0

Sequence)

PLL Locations in Stratix V Devices

Stratix V devices provide PLLs for the transceiver channels. These PLLs are located in a strip, where the strip

refers to an area in the FPGA.

The total number of PLLs in the Stratix V devices includes the PLLs in the PLL strip. However, the transceivers

can only use the PLLs located in the strip.

The following figures show the physical locations of the fractional PLLs. Every index represents one fractional

PLL in the device. The physical locations of the fractional PLLs correspond to the coordinates in the Quartus II

Chip Planner.

Clock Networks and PLLs in Stratix V Devices

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